EP1SGX10C Datasheet, PDF (103/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 68 and 69 show the memory block in input/output
clock mode.
Altera Corporation
103
Preliminary