EP1SGX10C Datasheet, PDF (226/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 109. Stratix GX Transceiver Reset & PLL Lock Time Parameters
Symbol
Min
Typ
Max
Units
t_{A N A L O G R E S E T P W} (5)
1
t_{D I G I TA L R E S E T P W} (5)
4
t_{T X _ P L L _ L O C K} (3)
t_{R X _ F R E Q L O C K} (4)
t_{R X _ F R E Q L O C K 2 P H A S E L O C K} (2)
mS
Parallel clock
cycle
10
µS
5
mS
2
mS
Notes to Table 109:
(1) The minimum pulse width specified is associated with the power-down of circuits.
(2) The clock recovery unit (CRU) phase locked-to-data time is based on a data rate of 500 Mbps and 8B/10B encoded
data.
(3) After #pll_areset, pll_enable, or PLL power-up, the time required for the transceiver PLL to lock to the
reference clock.
(4) After #rx_analogreset, the time for the CRU to switch to lock-to-data mode.
(5) There is no maximum pulse width specification. The GXB can be held in reset indefinitely.
Routing delays vary depending on the load on a specific routing line. The
Quartus II software reports the routing delay information when running
the timing analysis for a design. Contact Altera Applications Engineering
for more details.
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 126 shows the timing model for bidirectional IOE pin
timing. All registers are within the IOE.
226
Preliminary
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