EP1SGX10C Datasheet, PDF (228/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 111 shows the external I/O timing parameters when using regional
clock networks.
Table 111. Stratix GX Regional Clock External I/O Timing Parameters Notes (1), (2)
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
Parameter
Conditions
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by CLK pin
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by CLK pin
Clock-to-output delay output or bidirectional pin using
column IOE output register with regional clock fed by CLK
pin
C_{L O A D} = 10 pF
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
Clock-to-output delay output or bidirectional pin using
column IOE output register with regional clock Enhanced
PLL with default phase setting
C_{L O A D} = 10 pF
Notes to Table 111:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the
external timing for any pin.
Table 112 shows the external I/O timing parameters when using global
clock networks.
Table 112. Stratix GX Global Clock External I/O Timing Parameters (Part 1 of 2) Notes (1), (2)
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
Parameter
Conditions
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by CLK pin
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by CLK pin
Clock-to-output delay output or bidirectional pin using
C_{L O A D} = 10 pF
column IOE output register with global clock fed by CLK pin
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by Enhanced PLL with
default phase setting
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Preliminary
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