EP1SGX10C Datasheet, PDF (21/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Figure 14. External Termination & Biasing Circuit
50/60/75-Ω
Termination
Resistance
Receiver External Termination
and Biasing
V_DD
R1
C1
R1/R2 = 1K
V_DD × {R2/(R1 + R 2)} = 1.1 V
R2
Stratix GX Device
Receiver
RXIP
RXIN
Receiver External Termination
and Biasing
Transmission
Line
Programmable Equalizer
The programmable equalizer module boosts the high frequency
components of the incoming signal to compensate for losses in the
transmission medium. There are five possible equalization settings (0, 1,
2, 3, 4) to compensate for 0”, 10”, 20”, 30”, and 40” of FR4 trace. These
settings should be interpreted loosely. The programmable equalizer can
be set dynamically or statically.
Receiver PLL & CRU
Each transceiver block has four receiver PLLs and CRUs, each of which is
dedicated to a receive channel. If the receive channel associated with a
particular receiver PLL or CRU is not used, then the receiver PLL or CRU
is powered down for the channel. Figure 15 is a diagram of the receiver
PLL and CRU circuits.
Altera Corporation
21
Preliminary