EP1SGX10C Datasheet, PDF (54/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 39. PLL & Channel Layout in EP1SGX10 & EP1SGX25
Devices Notes (1), (2)
1 Receiver
1 Transmitter
11 Rows for
EP1SGX10 Devices
& 19 Rows for
EP1SGX25 Devices
1 Transmitter
1 Receiver
INCLK0
INCLK1
1 Receiver
1 Transmitter
11 Rows for
EP1SGX10 Devices
& 20 Rows for
EP1SGX25 Devices
8
Fast
PLL 1 (1)
Fast
PLL 2
Eight-Phase
Clock
8
1 Transmitter
1 Receiver
Notes to Figure 39:
(1) Fast PLL 1 in EP1SGX10 devices does not support DPA.
(2) Not all eight phases are used by the receiver channel or transmitter channel in non-
DPA mode.
54
Preliminary
Altera Corporation