EP1SGX10C Datasheet, PDF (30/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
8B/10B Decoder
The 8B/10B decoder converts the 10-bit encoded code group into 8-bit
data and 1 control bit. The 8B/10B decoder can be bypassed. The
following is a diagram of the conversion from a 10-bit encoded code
group into 8-bit data + 1-bit control.
Figure 22. 8B/10B Decoder Conversion
j hg f i e dc b a
9 87 65 4 3 21 0
MSB received last
8b-10b conversion
LSB received first
Parallel data 7 6 5 4 3
HG FE D
21
CB
0 ⁺ ctrl
A
There are two optional error status ports available in the 8B/10B decoder,
rx_errdetect and rx_disperr. Table 12 shows the values of the ports
from a given error. These status signals are aligned with the code group
in which the error occurred.
Table 12. Error Signal Values
Types of Errors
No errors
Invalid code groups
Disparity errors
rx_errdetect
1’b0
1’b1
1’b1
rx_disperr
1’b0
1’b0
1’b1
30
Preliminary
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