EP1SGX10C Datasheet, PDF (38/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 29. EP1SGX40G Device Inter-Transceiver & Global Clock Connections
IQ0 IQ1 IQ2
Transceiver Block 0
Global Clocks,
I/O Bus,
General Routing
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Transmitter
PLL
4
Receiver
PLLs (2)
Note (1)
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 1
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 4
IQ0
IQ1
refclkb
/2
IQ2
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 2
IQ0
IQ1
refclkb
/2
IQ2
Transmitter
PLL
4
Receiver
PLLs (2)
Transmitter
PLL
4
Receiver
PLLs (2)
Transmitter
PLL
4
Receiver
PLLs (2)
16
PLD
Global
Clocks
Global Clocks,
I/O Bus,
General Routing
Global Clocks,
I/O Bus,
General Routing
Transceiver Block 3
IQ0
IQ1
refclkb
/2
IQ2
Transmitter
PLL
4
Receiver
PLLs (2)
Notes to Figure 29:
(1) IQ lines are inter-transceiver block lines.
(2) There are four receiver PLLs in each transceiver block.
38
Preliminary
Altera Corporation