EP1SGX10C Datasheet, PDF (203/262 Pages) Altera Corporation – StratixGX FPGA Family

Operating Conditions
Table 70. 1.8-V I/O Specifications
Symbol
V_CCIO
V_{I H}
V_IL
V_OH
V_OL
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
I_OH = –2 to –8 mA (1)
I_OL = 2 to 8 mA (1)
Minimum Maximum
1.65
1.95
0.65 × V_CCIO 2.25
–0.3
0.35 × V_CCIO
V_CCIO – 0.45
0.45
Units
V
V
V
V
V
Table 71. 1.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum Maximum
V_CCIO
V_{I H}
V_IL
V_OH
V_OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
I_OH = –2 mA (1)
I_OL = 2 mA (1)
1.4
1.6
0.65 × V_CCIO V_CCIO + 0.3
–0.3
0.35 × V_CCIO
0.75 × V_CCIO
0.25 × V_CCIO
Note to Tables 67 through 71:
(1) Drive strength is programmable according to values in Table 45 on page 172.
Units
V
V
V
V
V
Figures 122 and 123 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V
PCML, LVPECL, and HyperTransport technology).
Altera Corporation
203
Preliminary