EP1SGX10C Datasheet, PDF (233/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 124. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2)
Symbol
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.000
4.887
2.000
5.247
2.000
6.011
ns
1.326
1.386
1.552
ns
0.000
0.000
0.000
ns
0.500
2.304
0.500
2.427
0.500
2.765
ns
Tables 125 through 130 show the external timing parameters on column
and row pins for EP1SGX40 devices.
Table 125. EP1SGX40 Column Pin Fast Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.704
2.912
3.235
ns
0.000
0.000
0.000
ns
2.000
5.060
2.000
5.432
2.000
6.226
ns
Table 126. EP1SGX40 Column Pin Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.467
2.671
3.011
ns
0.000
0.000
0.000
ns
2.000
5.255
2.000
5.673
2.000
6.501
ns
1.254
1.259
1.445
ns
0.000
0.000
0.000
ns
0.500
2.610
0.500
2.751
0.500
3.134
ns
Altera Corporation
233
Preliminary