EP1SGX10C Datasheet, PDF (83/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
RAM block and 4,608 bits for the M4K RAM block. The total number of
shift register outputs (number of taps n × width w) must be less than the
maximum data width of the RAM block (18 for M512 blocks, 36 for M4K
blocks). To create larger shift registers, the memory blocks are cascaded
together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 57 shows the TriMatrix
memory block in the shift register mode.
Figure 57. Shift Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
w
w
m-Bit Shift Register
w
m-Bit Shift Register
w
w
n Number
of Taps
w
m-Bit Shift Register
w
w
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The large number of M512 blocks are ideal for
designs with many shallow first-in first-out (FIFO) buffers. M4K blocks
provide additional resources for channelized functions that do not
require large amounts of storage. The M-RAM blocks provide a large
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Preliminary