EP1SGX10C Datasheet, PDF (16/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 7. Serializer
10
Low-speed
parallel clock
High-speed
serial clock
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
Serial data
D0
D0
out (to output
buffer)
Transmit Buffer
The Stratix GX transceiver buffers support the 1.5-V pseudo current
mode logic (PCML) I/O standard at a rate up to 3.1875 Gbps, across up to
40 inches of FR4 trace, and across 2 connectors. Additional I/O standards,
LVDS, 3.3-V PCML, LVPECL, can be supported when AC coupled. The
common mode of the Output Driver is 750 mV.
The output buffer, as shown in Figure 8, consists of a programmable
output driver and a programmable pre-emphasis circuit.
16
Preliminary
Altera Corporation