EP1SGX10C Datasheet, PDF (156/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
pin. The I/O standards supported by any particular bank determines
what standards are possible for an external clock output driven by the fast
PLL in that bank.
Table 41 shows the I/O standards supported by fast PLL input pins.
Table 41. Fast PLL Port Input Pin I/O Standards
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5V HSTL class I
1.5V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
SSTL-3 class II
AGP (1× and 2×)
CTT
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Input
PLLENABLE
v
v
156
Preliminary
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