EP1SGX10C Datasheet, PDF (94/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 62. M-RAM Block Control Signals
Dedicated
8
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
clocken_b
aclr_b
renwe_b
clock_a
clock_b
aclr_a
renwe_a
One of the M-RAM block’s horizontal sides drive the address and control
signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side
closest to the device perimeter contains the interfaces. The one exception
is when two M-RAM blocks are paired next to each other. In this case, the
side of the M-RAM block opposite the common side of the two blocks
contains the input interface. The top and bottom sides of any M-RAM
block contain data input and output interfaces to the logic array. The top
side has 72 data inputs and 72 data outputs for port B, and the bottom side
has another 72 data inputs and 72 data outputs for port A. Figure 63
shows an example floorplan for the EP1SGX40 device and the location of
the M-RAM interfaces.
94
Preliminary
Altera Corporation