EP1SGX10C Datasheet, PDF (227/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Figure 126. External Timing in Stratix GX Devices
Dedicated
Clock
OE Register
PRN
DQ
CLRN
Output Register
PRN
DQ
CLRN
Input Register
PRN
DQ
CLRN
t_INSU
t_INH
t_OUTCO
Bidirectional
Pin
All external I/O timing parameters shown are for 3.3-V LVTTL or
LVCMOS I/O standards with the maximum current strength. For
external I/O timing using standards other than LVTTL or LVCMOS use
the I/O standard input and output delay adders in Tables 131 through
135.
Table 110 shows the external I/O timing parameters when using fast
regional clock networks.
Table 110. Stratix GX Fast Regional Clock External I/O Timing Parameters Notes (1), (2)
Symbol
t_INSU
t_INH
t_OUTCO
Parameter
Setup time for input or bidirectional pin using column IOE
input register with fast regional clock fed by FCLK pin
Hold time for input or bidirectional pin using column IOE
input register with fast regional clock fed by FCLK pin
Clock-to-output delay output or bidirectional pin using
column IOE output register with fast regional clock fed by
FCLK pin
Conditions
C_{L O A D} = 10 pF
Notes to Table 110:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device
and speed grade and whether it is t_CO or t_SU. Designers should use the Quartus II software to verify the external
timing for any pin.
Altera Corporation
227
Preliminary