EP1SGX10C Datasheet, PDF (7/262 Pages) Altera Corporation – StratixGX FPGA Family

FPGA Functional Description
Figure 2. Stratix GX Block Diagram
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
IOEs
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M-RAM Block
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DSP
Block
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 5 lists the
resources available in Stratix GX devices.
Table 5. Stratix GX Device Resources
Device
M512 RAM
M4K RAM
Columns/Blocks Columns/Blocks
EP1SGX10
EP1SGX25
EP1SGX40
4 / 94
6 / 224
8 / 384
2 / 60
3 / 138
3 / 183
M-RAM
Blocks
1
2
4
DSP Block
Columns/Blocks
2/6
2 / 10
2 / 14
LAB
Columns
40
62
77
LAB Rows
30
46
61
Altera Corporation
7
Preliminary