EP1SGX10C Datasheet, PDF (107/262 Pages) Altera Corporation – StratixGX FPGA Family

Digital Signal Processing Block
Figure 71. Single-Port Mode
8 LAB Row
Clocks
8
data[ ]
address[ ]
wren
outclken
inclken
inclock
outclock
DQ
ENA
DQ
ENA
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
Address
DQ
ENA
Write Enable
DQ
ENA
Write
Pulse
Generator
To MultiTrack
Interconnect
Digital Signal
Processing
Block
Altera Corporation
The most commonly used DSP functions are finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, direct cosine transform (DCT)
functions, and correlators. All of these blocks have the same fundamental
building block: the multiplier. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Stratix GX devices provide DSP blocks to meet the arithmetic
requirements of these functions.
Each Stratix GX device has two columns of DSP blocks to efficiently
implement DSP functions faster than LE-based implementations. Larger
Stratix GX devices have more DSP blocks per column (see Table 33). Each
DSP block can be configured to support up to:
■ Eight 9 × 9-bit multipliers
■ Four 18 × 18-bit multipliers
■ One 36 × 36-bit multiplier
As indicated, the Stratix GX DSP block can support one 36 × 36-bit
multiplier in a single DSP block. This is true for any matched sign
multiplications (either unsigned by unsigned or signed by signed), but
107
Preliminary