EP1SGX10C Datasheet, PDF (10/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains the following:
■ Transmitter PLL
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel to serial converter)
■ Transmitter output buffer
The receiver contains the following:
■ Input buffer
■ Clock recovery unit (CRU)
■ Deserializer
■ Pattern detector and word aligner
■ Rate matcher and channel aligner
■ 8B/10B decoder
■ Receiver logic array interface
Designers can set all the Stratix GX transceiver functions through the
Quartus II software. Designers can set programmable pre-emphasis,
programmable equalizer, and programmable V_OD dynamically as well.
Each Stratix GX transceiver channel is also capable of BIST generation
and verification in addition to various loopback modes. Figure 4 shows
the block diagram for the Stratix GX transceiver channel.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10-gigabit XAUI and GigE. The PCS portion of the transceiver consists of
the logic array interface, 8B/10B encoder/decoder, pattern detector, word
aligner, rate matcher, channel aligner, and the BIST and pseudo-random
binary sequence pattern generator/verifier. The PMA portion of the
transceiver consists of the serializer/deserializer, the CRU, and the I/O
buffers.
10
Preliminary
Altera Corporation