EP1SGX10C Datasheet, PDF (42/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 33. EP1SGX40 Receiver PLL Recovered Clock to Fast Regional Clock
Connection
PLD
Stratix GX
FCLK[1..0] Transceiver Blocks
Block 0
Block 1
Block 4
Block 2
Block 3
FCLK[1..0]
Table 15 summarizes the possible clocking connections for the
transceivers.
Table 15. Possible Clocking Connections for Transceivers (Part 1 of 2)
Source
REFCLKB
Transmitter PLL
Receiver PLL
GCLK
RCLK
FCLK
Transmitter
PLL
v
v
v
v
Receiver
PLL
v
v
v
v
v
Destination
GCLK
v (1)
v
v
RCLK
v
v
v
FCLK
v
v
IQ Lines
v (1)
42
Preliminary
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