EP1SGX10C Datasheet, PDF (13/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
The transmitter PLL can support up to 3.1875 Mbps. The input clock
frequency for –5 and –6 speed grade devices is limited to 650 MHz if
designers use the REFCLKB pin or to 325 MHz if designers use the other
clock routing resources. For –7 speed grade devices, the maximum input
clock frequency is 312.5 MHz with the REFCLKB pin, and the maximum
is 156.25 MHz for all other clock routing resources. An optional
PLL_LOCKED port is available to indicate whether the transmitter PLL is
locked to the reference clock. The transmitter PLL has a programmable
loop bandwidth that can be set to low or high. The loop bandwidth
parameter can be statically set in the Quartus II software.
Table 7 lists the adjustable parameters in the transmitter PLL.
Table 7. Transmitter PLL Specifications
Parameter
Input reference frequency range
Data rate support
Multiplication factor (W)
Bandwidth
Specifications
25 MHz to 650 MHz
500 Mbps to 3.1875 Gbps
2, 4, 5, 8, 10, 16, or 20 (1)
Low, high
Note to Table 7:
(1) Multiplication factors 2 and 5 can only be achieved with the use of the pre-divider
on the REFCLKB pin.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer resides in the
transceiver block at the PLD boundary. This FIFO buffer compensates for
the phase differences between the transmitter reference clock (inclk)
and the PLD interface clock (tx_coreclk). The phase difference
between the two clocks must be less than 360°. The PLD interface clock
must also be frequency locked to the transmitter reference clock. The
phase compensation FIFO buffer is four words deep and cannot be
bypassed.
Byte Serializer
The byte serializer takes double-width words (16 or 20 bits) from the PLD
interface and converts them to a single width word (8 or 10 bits) for use
in the transceiver. The transmit data path after the byte serializer is single
width (8 or 10 bits). The byte serializer is bypassed when single width
mode (8 or 10 bits) is used at the PLD interface.
Altera Corporation
13
Preliminary