EP1SGX10C Datasheet, PDF (240/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 135. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
I/O Standard
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
-5 Speed Grade
Min
Max
1,993
1,773
1,553
1,493
1,423
2,631
2,051
1,941
1,901
4,632
3,542
3,472
6,620
6,040
5,570
1,191
1,231
1,111
1,111
1,111
1,311
1,311
1,391
1,431
1,291
1,912
1,832
3,097
2,867
4,916
4,726
3,247
3,257
-6 Speed Grade
Min
Max
2,097
1,866
1,635
1,572
1,498
2,768
2,159
2,043
2,001
4,873
3,728
3,655
6,964
6,355
5,862
1,255
1,297
1,171
1,171
1,171
1,381
1,381
1,465
1,507
1,360
2,013
1,929
3,260
3,018
5,174
4,975
3,417
3,428
-7 Speed Grade
Unit
Min
Max
2,411
ps
2,145
ps
1,879
ps
1,807
ps
1,722
ps
3,182
ps
2,482
ps
2,349
ps
2,300
ps
5,604
ps
4,287
ps
4,203
ps
8,008
ps
7,307
ps
6,740
ps
1,442
ps
1,90
ps
1,346
ps
1,346
ps
1,346
ps
1,587
ps
1,587
ps
1,684
ps
1,732
ps
1,563
ps
2,314
ps
2,218
ps
3,748
ps
3,470
ps
5,950
ps
5,721
ps
3,929
ps
3,941
ps
240
Preliminary
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