EP1SGX10C Datasheet, PDF (241/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 136. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins
I/O Standard
LVCMOS
2 mA
4 mA
8 mA
12 mA
3.3-V LVTTL
4 mA
8 mA
12 mA
16 mA
2.5-V LVTTL
2 mA
8 mA
12 mA
16 mA
1.8-V LVTTL
2 mA
8 mA
12 mA
1.5-V LVTTL
2 mA
4 mA
8 mA
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS (1)
LVPECL (1)
3.3-V PCML (1)
HyperTransport technology (1)
-5 Speed Grade
Min
Max
1,930
1,930
1,710
1,490
1,953
1,733
1,513
1,453
2,632
2,052
1,942
1,902
4,537
3,447
3,377
6,575
5,995
5,525
1,410
1,450
1,310
1,797
1,717
1,340
1,400
1,300
1,430
-6 Speed Grade
Min
Max
2,031
2,031
1,800
1,569
2,055
1,824
1,593
1,530
2,769
2,160
2,044
2,002
4,773
3,628
3,555
6,917
6,308
5,815
1,485
1,527
1,380
1,892
1,808
1,411
1,474
1,369
1,506
-7 Speed Grade
Unit
Min
Max
2,335
ps
2,335
ps
2,069
ps
1,803
ps
2,363
ps
2,097
ps
1,831
ps
1,759
ps
3,183
ps
2,483
ps
2,350
ps
2,301
ps
5,489
ps
4,172
ps
4,088
ps
7,954
ps
7,253
ps
6,686
ps
1,707
ps
1,755
ps
1,586
ps
2,175
ps
2,079
ps
1,622
ps
1,694
ps
1,573
ps
1,731
ps
Note to Tables 131 through 136:
(1) These parameters are only available on the left side row I/O pins.
Altera Corporation
241
Preliminary