HD6417705 Datasheet, PDF (93/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Instruction Format
d type
15
0
xxxx xxxx dddd dddd
Source
Operand
dddddddd: GBR
indirect with
displacement
Destination
Operand
Sample Instruction
R0 (register direct) MOV.L @(disp,GBR),R0
d12 type
15
0
xxxx dddd dddd dddd
R0 (register direct) dddddddd: GBR
indirect with
displacement
MOV.L R0,@(disp,GBR)
dddddddd:
PC-relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0
dddddddd:
—
PC-relative
BF label
dddddddddddd: —
PC-relative
BRA label
(label=disp+PC)
nd8 type
15
0
xxxx nnnn dddd dddd
dddddddd: PC-
relative with
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
i type
15
0
xxxx xxxx i i i i i i i i
iiiiiiii: immediate
Indexed GBR
indirect
AND.B #imm,@(R0,GBR)
ni type
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: immediate
iiiiiiii: immediate
iiiiiiii: immediate
R0 (register direct) AND #imm,R0
—
TRAPA #imm
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00, 09/03, page 47 of 690