HD6417705 Datasheet, PDF (115/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
Area P0
cacheable
External address space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Area U0
cacheable
Area P1
cacheable
Area P2
non-cacheable
Area P3
cacheable
Address error
Area P4
non-cacheable
Privileged mode
User mode
Figure 3.3 Virtual Address Space (MMUCR.AT = 0)
H'0000 0000
H'8000 0000
H'FFFF FFFF
H'E000 0000
Reserved area
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
Cache address array
Cache data array
TLB address array
TLB data array
Reserved area
H'FC00 0000
H'FFFF FFFF
Control register area
Figure 3.4 P4 Area
Rev. 2.00, 09/03, page 69 of 690