HD6417705 Datasheet, PDF (325/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

9.4 Register Descriptions
The CPG has the following registers. Refer to section 24, List of Registers, for the addresses of the
registers and the state of each register in each processor state.
• Frequency control register (FRQCR)
• USB clock control register (UCLKCR)
9.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify
whether a clock is output from the CKIO pin, the on/off state of PLL circuit 1, PLL standby, the
frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal
clock and the peripheral clock. Only word access can be used on FRQCR. As for the combination
of the clock rate, refer to table 9.3. The combinations listed in table 9.3 should only be set on
FRQCR.
Bit
Bit
Name
15 to 13 
Initial
Value R/W
0
R
12
CKOEN 1
R/W
11, 10 
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies to output a clock from the CKIO pin or to fix
the CKIO pin low when software standby is canceled
(after an interrupt before STATUS1 becomes low and
STATUS0 becomes low). The CKIO pin is fixed low
during STATUS1 = low and STATUS0 = high, when
the CKOEN bit is cleared to 0. Therefore, the
malfunction of an external circuit because of an
unstable CKIO clock in releasing software standby
mode can be prevented.
In clock operating mode 7, the CKIO pin is in the input
state regardless of this bit.
0: Fixes the CKIO pin low in software standby mode.
1: Outputs a clock from the CKIO pin.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00, 09/03, page 279 of 690