HD6417705 Datasheet, PDF (90/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Addressing
Mode
PC-relative
Instruction
Format Effective Address Calculation Method
disp:8
Effective address is PC with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
PC
disp
+
(sign-extended)
×
PC + disp × 2
Calculation
Formula
PC + disp × 2
disp:12
2
Effective address is PC with 12-bit displacement PC + disp × 2
disp added after being sign-extended and
multiplied by 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Rn
Effective address is sum of PC and Rn.
PC
PC + Rn
+
PC + Rn
Rn
Immediate
#imm:8 8-bit immediate data imm of TST, AND, OR,
—
or XOR instruction is zero-extended.
#imm:8 8-bit immediate data imm of MOV, ADD, or
—
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction —
is zero-extended and multiplied by 4.
Note:
For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the
operand size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
@ (disp:4, Rn)
; Register indirect with displacement
@ (disp:8, Rn)
; GBR indirect with displacement
@ (disp:8, PC)
; PC relative with displacement
disp:8, disp
; PC relative
Rev. 2.00, 09/03, page 44 of 690