HD6417705 Datasheet, PDF (367/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

12.5 Interrupts
There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using
the input capture function (TICPI2).
12.5.1 Status Flag Set Timing
The UNF bit is set to 1 when the TCNT underflows. Figure 12.7 shows the timing.
Pφ
TCNT
Underflow
signal
UNF
TUNI
H'00000000
TCOR value
Figure 12.7 UNF Set Timing
12.5.2 Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 12.8 shows the timing.
TCR write cycle
T₁
T₂
T₃
Pφ
Peripheral address bus
TCR address
UNF, ICPF
Figure 12.8 Status Flag Clear Timing
Rev. 2.00, 09/03, page 321 of 690