HD6417705 Datasheet, PDF (308/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
RD
WEn
DACKn
(Active-Low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 8.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)
• Single Address Mode
In single address mode, either the transfer source or transfer destination peripheral device is
accessed (selected) by means of the DACK signal, and the other device is accessed by address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in
the case of transfer between external memory and an external device with DACK shown in
figure 8.7, when the external device outputs data to the data bus, that data is written to the
external memory in the same bus cycle.
Rev. 2.00, 09/03, page 262 of 690