HD6417705 Datasheet, PDF (350/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

In Case of Canceling Software Standby:
a. Canceling software standby by interrupt
Oscillation stops
Interrupt request WDT overflow
CKIO
STATUS
Normal^*2
Standby^*1
WDT count
Normal^*2
Notes: 1. Standby: LH (STATUS1 low, STATUS0 high)
2. Normal: LL (STATUS1 low, STATUS0 low)
Figure 11.4 Canceling Software Standby by Interrupt STATUS Output
b. Canceling software standby by power-on reset
CKIO
RESETP ^*1
Oscillation stops Reset
STATUS
Normal^*5
Standby^*4 *2
Reset^*3
Normal^*5
0 to 10 Bcyc^*6
0 to 30 Bcyc^*6
Notes: 1. When software standby mode is cleared with a power-on reset, the WDT does
not count. Keep RESETP low during the PLL’s oscillation settling time.
2. Undefined
3. Reset: HH (STATUS1 high, STATUS0 high)
4. Standby: LH (STATUS1 low, STATUS0 high)
5. Normal: LL (STATUS1 low, STATUS0 low)
6. Bcyc: Bus clock cycle
Figure 11.5 Canceling Software Standby by Power-On Reset STATUS Output
Rev. 2.00, 09/03, page 304 of 690