HD6417705 Datasheet, PDF (11/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Main Revisions and Additions in this Edition
Item
1.1 SH7705 Features
Table 1.1 SH7705
Features
1.3 Pin Assignment
Table 1.2 Pin Functions
Page
4
Revisions (See Manual for Details)
Features of USB function module (USB) amended
• Conforms to USB 2.0 full-speed specification
13, 15, Note *6, *7 added
16
Pin No.
FP-
208C
139
TBP-
208A
G15
Pin Name
TDI^*7/PTG0
I/O
I / I/O
140 G14 TCK^*7/PTG1
I / I/O
141 F17 TMS^*7/PTG2
I / I/O
142 F16 TRST^{*1 *7}/PTG3 I / I/O
143 F15 TDO/PTF5
O / I/O
144 F14 ASEBRKAK/
PTF6
O / I/O
145 E17 ASEMD0^{*2 *7}/ I / I/O
PTF7
195 C6
RESETP^*6
I
Description
Test data input (UDI) /
input/output port G
Test clock (UDI) / input/output
port G
Test mode select (UDI) /
input/output port G
Test reset (UDI) / input/output
port G
Test data output (UDI) /
input/output port F
ASE break acknowledge
(UDI) / input/output port F
ASE mode (UDI) / input/output
port F
Power-on reset request
4.4.1 Address Array
105
Address-Array Write
(Associative Operation)
4.4.3 Usage Examples
107
Invalidating a Specific Entry
Invalidating an Address
108
Specification
5.2.5 Exception Source 117
Acceptance Timing and
Priority
Table 5.1 Exception Event
Vectors
Notes: 6. Pull-up MOS connected.
7. The pull-up MOS turns on if the pin function controller
(PFC) is used to select other functions (UDI).
Description amended
⋅⋅⋅⋅⋅ This operation is used to invalidate the address
specification for a cache.
Description largely revised
Description added
Note *3 amended
Note: 3. If an interrupt is accepted, the exception event
register (EXPEVT) is not changed. ⋅⋅⋅⋅⋅
Rev. 2.00, 09/03, page xi of xlvi