HD6417705 Datasheet, PDF (392/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 14.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing performed
by compare match B), and settings have been made so that output is toggled by compare match A.
TCNT value
H'FFFF
TGRB
TGRA
H'0000
Counter cleared by TGRB compare match
Time
TO pin
Toggle output
Figure 14.7 Example of Toggle Output Operation
14.4.3 Buffer Operation
Buffer operation, enables TGRC and TGRD to be used as buffer registers.
Table 14.6 shows the register combinations used in buffer operation.
Table 14.6 Register Combinations in Buffer Operation
Timer General Register
TGRA
TGRB
Buffer Register
TGRC
TGRD
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. For update timing from a buffer register, rewriting on
compare match occurrence or on counter cleaning can be selected.
This operation is illustrated in figure 14.8.
Counter clearing signal
BFWT bit
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 14.8 Compare Match Buffer Operation
Rev. 2.00, 09/03, page 346 of 690