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HD6417705 Datasheet, PDF (100/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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Table 2.7 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC
Rm,Rn
ADDV
Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1
Rm,Rn
DIV0S
Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
Instruction Code Operation
Privileged
Mode
Cycles T Bit
0011nnnnmmmm1100 Rn+RmâRn
â
1
â
0111nnnniiiiiiii
Rn+immâRn
â
1
â
0011nnnnmmmm1110 Rn+Rm+TâRn, CarryâT
â
1
Carry
0011nnnnmmmm1111 Rn+RmâRn, OverflowâT
â
1
Overflow
10001000iiiiiiii
If R0 = imm, 1 â T
â
1
Comparison
result
0011nnnnmmmm0000 If Rn = Rm, 1 â T
â
1
Comparison
result
0011nnnnmmmm0010 If Rn ⥠Rm with unsigned data, 1 â
âT
1
Comparison
result
0011nnnnmmmm0011 If Rn ⥠Rm with signed data, 1 â â
T
1
Comparison
result
0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 â
âT
1
Comparison
result
0011nnnnmmmm0111 If Rn > Rm with signed data, 1 â â
T
1
Comparison
result
0100nnnn00010101 If Rn ⥠0, 1 â T
â
1
Comparison
result
0100nnnn00010001 If Rn > 0, 1 â T
â
1
Comparison
result
0010nnnnmmmm1100 If Rn and Rm have an equivalent â
byte, 1 â T
1
Comparison
result
0011nnnnmmmm0100 Single-step division (Rn/Rm) â
1
Calculation
result
0010nnnnmmmm0111 MSB of Rn â Q, MSB of Rm â â
M, M ^ Q â T
1
Calculation
result
0000000000011001 0 â M/Q/T
â
1
0
0011nnnnmmmm1101 Signed operation of Rn à Rm â â
MACH, MACL 32 Ã 32 â 64 bits
2 (to â
5)*
0011nnnnmmmm0101 Unsigned operation of Rn à Rm â
â MACH, MACL 32 Ã 32 â 64
bits
2 (to â
5)*
0100nnnn00010000
Rn â 1 â Rn, if Rn = 0, 1 â T, â
else 0 â T
1
Comparison
result
Rev. 2.00, 09/03, page 54 of 690
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