HD6417705 Datasheet, PDF (702/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn^*2
Td1
Td2 Td3
Td4
Tp
Tpw Tr
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
Row address
t_AD1
t_CSD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
t_AD1
(1-4)
Read command
t_AD1
t_AD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1 t_RASD1 t_RASD1 t_RASD1
t_CASD1
t_DQMD1
t_CASD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1 t_DQMD1
t_BSD
t_RDS2 t_RDH2
t_BSD
t_RDS2 t_RDH2
t_BSD
t_DACD
(High)
t_DACD
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACTV + READ Commands,
Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)
Rev. 2.00, 09/03, page 656 of 690