HD6417705 Datasheet, PDF (75/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

H'0000 0000
P0 area
External memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P1 area
P2 area
P3 area
P4 area
Privileged mode
H'8000 0000
Address error
User mode
H'FFFF FFFF
Figure 2.2 Logical Address to External Memory Space Mapping
2.3 Register Descriptions
This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three
system registers, and one program counter.
General Registers: This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0,
R0_BANK1 to R7_BANK1 and R8 to R15. R0 to R7 are banked. The process mode and the
register bank (RB) bit in the status register (SR) define which set of banked registers (R0_BANK0
to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers.
System Registers: This LSI incorporates the multiply and accumulate registers (MACH/MACL)
and procedure register (PR) as system registers. These registers can be accessed regardless of the
processing mode.
Program Counter: The program counter stores the value obtained by adding 4 to the current
instruction address.
Control Registers: This LSI incorporates the status register (SR), global base register (GBR),
save status register (SSR), save program counter (SPC), and vector base register (VBR) as control
register. Only the GBR can be accessed in user mode. Control registers other than the GBR can be
accessed only in privileged mode.
Rev. 2.00, 09/03, page 29 of 690