HD6417705 Datasheet, PDF (455/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 16.4 shows an example of the operation for transmission in asynchronous mode.
1
Serial
data
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D7 0/1 1 0 D0
Data
Parity Stop
bit bit
D1
D7 0/1 1
1
Idle state
(mark state)
TDFE
TEND
TXI interrupt
request
Data written to SCFTDR
and TDFE flag read as
1 and then cleared to 0
by TXI interrupt handler
TXI interrupt
request
One frame
Figure 16.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
• Transmit Data Stop Function
When a value in the SCTDSR register is matched with the number of transmit data bytes, this
function stops the transmit operation. Interrupts can be generated and the DMAC can be activated
by setting the TSIE bit (interrupt enable bit).
Figure 16.5 shows an example of operation for the transmit data stop function.
Transmit data
TxD
Start
bit
0 D0 D1
Parity Stop
bit bit
D6 D7 0/1
Start
bit
0 D0 D1
D6 D7 0/1
TSF flag
Figure 16.5 Example of Transmit Data Stop Function
Rev. 2.00, 09/03, page 409 of 690