HD6417705 Datasheet, PDF (82/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Initial
Bit Bit Name Value R/W Description
9
M
8
Q

R/W M Bit

R/W Q Bit
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user mode by
using the DIV0S, DIV0U, and DIV1 instructions. These bits
are undefined at reset. These bits do not change in an
exception handling state.
7 to 4 I3 to I0 1
R/W Interrupt Mask
Indicates the interrupt mask level. These bits do not change
even if an interrupt occurs. At reset, these bits are initialized
to B’1111. These bits are not affected in an exception
handling state.
3, 2 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
S

R/W Saturation Mode
Specifies the saturation mode for multiply instructions or
multiply and accumulate instructions. This bit can be specified
by the SETS and CLRS instructions in user mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
0
T

R/W T Bit
Indicates true or false for compare instructions or carry or
borrow occurrence for an operation instruction with carry or
borrow. This bit can be specified by the SETT and CLRT
instructions in user mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
can be read or written in privileged mode.
Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged
mode. Before entering the exception, the contents of the SR register is stored in the SSR register.
At reset, the SSR initial value is undefined.
Save Program Counter (SPC): The save program counter (SPC) can be accessed only in
privileged mode. Before entering the exception, the contents of the PC are stored in the SPC. At
reset, the SPC initial value is undefined.
Global Base Register (GBR): The global base register (GBR) is referenced as a base register in
GBR indirect addressing mode. At reset, the GBR initial value is undefined.
Rev. 2.00, 09/03, page 36 of 690