HD6417705 Datasheet, PDF (260/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.4 Single Read
A read access ends in one cycle when data exists in non-cacheable region and the data bus width is
larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst
read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles
are generated even when a cache-through area is accessed.
Figure 7.17 shows the basic timing chart for single read.
Tr
Tc1
Tw
Td1
Tde
Tap
CKIO
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL
3. The waveform for DACKn is when active low is specified.
Figure 7.17 Basic Timing for Single Read (Auto Precharge)
Rev. 2.00, 09/03, page 214 of 690