HD6417705 Datasheet, PDF (515/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.7.3 DMA Transfer for Endpoint 2
When the transmit data at EP2 is transferred by the DMAC, the USB function module
automatically performs the same processing as writing 1 to the PKTE bit in TRG if the currently
selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the
user need not write 1 to the PKTE bit. To transfer data of less than 64 bytes, the user must write 1
to the PKTE bit using the DMA transfer end interrupt of the on-chip DMAC. If the user writes 1 to
the PKTE bit when the maximum number of bytes (64 bytes) are transferred, correct operation
cannot be guaranteed.
Figure 18.16 shows an example for transmitting 150 bytes of data to the host. In this case, internal
processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed
twice. This internal processing is performed when the currently selected data FIFO becomes full.
Accordingly, this processing is automatically performed only when 64-byte data is sent.
When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit is not
performed, and the user must write 1 to the PKTE bit by software. In this case, the application has
no more data to transfer but the USB function module continues to output DMA requests for EP2
as long as the FIFO has an empty space. When all data has been transferred, write 0 to the
EP2DMAE bit in DMAR to cancel DMA requests for EP2.
64 bytes
64 bytes
22 bytes
PKTE
(Automatically
performed)
PKTE
PKTE is
(Automatically not performed
performed)
Execute by DMA transfer
end interrupt (user)
Figure 18.16 PKTE Bit Operation for EP2
Rev. 2.00, 09/03, page 469 of 690