HD6417705 Datasheet, PDF (495/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.16 Data Status Register (DASTS)
DASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is
written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all
data has been transmitted to the host.
Bit Bit Name
7, 6 
5
EP3DE
4
EP2DE
3 to 1 
0
EP0iDE
Initial Value R/W
0
R
0
R
0
R
0
R
0
R
Description
Reserved
This bit is always read as 0.
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data.
Reserved
This bit is always read as 0.
EP0i Data Present
This bit is set when the endpoint 0 FIFO buffer
contains valid data.
18.3.17 FIFO Clear Register (FCLR)
FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit Bit Name
7

6
EP3CLR
5
EP1CLR
Initial Value R/W
Undefined 
Undefined W
Undefined W
Description
Reserved
The write value should always be 0.
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
Rev. 2.00, 09/03, page 449 of 690