HD6417705 Datasheet, PDF (714/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.7 DMAC Signal Timing
Table 25.9 DMAC Signal Timing
(Conditions: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to
1.6 V, AVCC = 3.0 to 3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-PLL2 =
AVSS = 0 V, Ta = –20 to 75°C)
Module Item
Symbol Min Max
Unit Figure
DMAC DREQ setup time
tDRQS
10
—
ns
25.43
DREQ hold time
tDRQH
3
—
DACK, TEND delay time
tDACD
—
10
25.44
CKIO
DREQn
t_{DRQS tDRQH}
Figure 25.43 DREQ Input Timing
CKIO
TEND0
DACKn
t_DACD
t_DACD
Figure 25.44 DACK, TEND Output Timing
Rev. 2.00, 09/03, page 668 of 690