HD6417705 Datasheet, PDF (435/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.3.7 FIFO Error Count Register (SCFER)
SCFER is a 16-bit read-only register that indicates the number of receive errors (framing or parity
error).
Bit
15, 14
Bit
Name

13 to 8
PER5
to
PER0
7, 6

5 to 0
FER5
to
FER0
Initial
Value
0
0
0
0
R/W
R
R
R
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Parity Error Count
Indicates the number of data, in which parity errors are
generated, in receive data stored in the receive FIFO
data register (SCFRDR) in asynchronous mode.
After setting the ER bit in SCSSR, the value of bits 13
to 8 indicates the number of parity error generated data.
When all 64 bytes of receive data in SCFRDR have
parity errors, the PER5 to PER0 bits indicate 0.
Reserved
These bits are always read as 0. The write value should
always be 0.
Framing Error Count
Indicates the number of data, in which framing errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
After setting the ER bit in SCSSR, the value of bits 5 to
0 indicates the number of framing error generated data.
When all 64 bytes of receive data in SCFRDR have
framing errors, the FER5 to FER0 bits indicate 0.
Rev. 2.00, 09/03, page 389 of 690