HD6417705 Datasheet, PDF (310/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of
channel control register (CHCR).
a. Cycle-Steal Mode
• Normal mode
In the normal mode of cycle-steal, the bus right is given to another bus master after a one-
transfer-unit (byte, word, long-word, or 16 bytes unit) DMA transfer. When another transfer
request occurs, the bus rights are obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus right is passed to the other
bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request
source, transfer source, and transfer destination. Figure 8.9 shows an example of DMA transfer
timing in cycle steal mode. Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
Bus right returned to CPU once
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read/Write
Read/Write
Figure 8.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
• Intermittent Mode 16 and Intermittent Mode 64
In intermittent mode of cycle steal, DMAC returns the bus right to other bus master whenever
a unit of transfer (byte, word, longword, or 16 bytes) is complete. If the next transfer request
occurs after that, DMAC gets the bus right from other bus master after waiting for 16 or 64
clocks in Bφ count. DMAC then transfers data of one unit and returns the bus right to other bus
master. These operations are repeated until the transfer end condition is satisfied. It is thus
possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of
cycle steal.
When DMAC gets again the bus right, DMA transfer can be postponed in case of entry
updating due to cache miss.
This intermittent mode can be used for all transfer section; transfer requester, source, and
destination. The bus modes, however, must be cycle steal mode in all channels.
Rev. 2.00, 09/03, page 264 of 690