HD6417705 Datasheet, PDF (388/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.4 Operation
14.4.1 Overview
Operation in each mode is outlined below.
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,
and is also capable of free-running operation and periodic counting.
Buffer Operation: When a compare match occurs, the value in the buffer register for the relevant
channel is transferred to TGR. For update timing from a buffer register, rewriting on compare
match occurrence or on counter clearing can be selected.
PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of
TIOR. A PWM waveform with a duty cycle of between 0% and 100% can be output, according to
the setting of each TGR register.
Rev. 2.00, 09/03, page 342 of 690