HD6417705 Datasheet, PDF (386/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.3.5 Timer Status Registers (TSR)
TSR are 16-bit registers that indicate the status of each channel.
Initial
Bit
Bit Name Value R/W Description
15 to 5 
0
R
Reserved
These bits are always read as 0 and cannot be modified.
4
TCFV
0
R/(W)^* Overflow Flag
Status flag that indicates that TCNT overflow has occurred.
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to
H'0000)
3
TGFD
0
R/(W)^* Output Compare Flag D
Status flag that indicates the occurrence of TGRD compare
match.
[Clearing condition]
When 0 is written to TGFD after reading TGFD = 1
[Setting condition]
When TCNT = TGRD
2
TGFC
0
R/(W)^* Output Compare Flag C
Status flag that indicates the occurrence of TGRC compare
match.
[Clearing condition]
When 0 is written to TGFC after reading TGFC = 1
[Setting condition]
When TCNT = TGRC
1
TGFB
0
R/(W)^* Output Compare Flag B
Status flag that indicates the occurrence of TGRB compare
match.
[Clearing condition]
When 0 is written to TGFB after reading TGFB = 1
[Setting condition]
When TCNT = TGRB
Rev. 2.00, 09/03, page 340 of 690