HD6417705 Datasheet, PDF (197/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.2 Pin Configuration
Table 7.1 Pin Configuration
Name
I/O
A25 to A0
O
D31 to D0
I/O
BS
O
CS0, CS2 to CS4, O
CS5A, CS5B, CS6A,
CS6B
RD/WR
O
RD
O
WE3,
O
DQMUU
WE2,
O
DQMUL
WE1,
O
DQMLU
WE0,
O
DQMLL
RASU
O
RASL
CASU
O
CASL
Function
Address bus
Data bus
Bus cycle start
Asserted when a normal space, byte-selection SRAM, burst ROM, or
address/data multiplex I/O is accessed. Asserted by the same timing
as CAS in SDRAM access.
Chip select
Read/write
Connects to WE pins when SDRAM or byte-selection SRAM is
connected.
Read
Indicates that D31 to D24 are being written to when a normal space
is set.
Selects D31 to D24 when a byte-selection SRAM space is set.
Selects D31 to D24 when an SDRAM space is set.
Indicates that D23 to D16 are being written to when a normal space
is set.
Selects D23 to D16 when a byte-selection SRAM space is set.
Selects D23 to D16 when an SDRAM space is set.
Indicates that D15 to D8 are being written to when a normal space
and address/data multiplex I/O space are set.
Selects D15 to D8 when a byte-selection SRAM space is set.
Selects D15 to D8 when an SDRAM space is set.
Indicates that D7 to D0 are being written to when a normal space
and address/data multiplex I/O space are set.
Selects D7 to D0 when a byte-selection SRAM space is set.
Selects D7 to D0 when an SDRAM space is set.
Connects to RAS pin when SDRAM is connected.
Connects to CAS pin when SDRAM is connected.
Rev. 2.00, 09/03, page 151 of 690