HD6417705 Datasheet, PDF (412/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2, 1
—
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
AF
0
R/W Alarm Flag
The AF flag is set to 1 when the alarm time set in
an alarm register (only registers with ENB bit of
the corresponding alarm registers and YAEN bit
in RCR3 set to 1) matches the clock and calendar
time. This flag is cleared to 0 when 0 is written,
but holds the previous value when 1 is written.
0: Clock/calendar and alarm register have not
matched.
[Clearing condition] When 0 is written to AF
1: [Setting condition] Clock/calendar and alarm
register have matched (only registers that ENB
bit and YAEN bit is 1)
15.3.17 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit readable/writable register for periodic interrupt
control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is
initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a
manual reset. It is not initialized in standby mode, and retains its contents.
Bit
Bit Name Initial Value R/W Description
7
PEF
0
R/W Periodic Interrupt Flag
Indicates interrupt generation with the period
designated by the PES2 to PES0 bits. When set
to 1, PEF generates periodic interrupts.
0: Interrupts not generated with the period
designated by the PES bits.
[Clearing condition] When 0 is written to PEF
1: [Setting condition] When interrupts are
generated with the period designated by the
PES bits or 1 is written to PEF
Rev. 2.00, 09/03, page 366 of 690