HD6417705 Datasheet, PDF (148/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated to indicate that the hit way is the most recently hit way.
Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown
in table 4.3. Entries are updated in 16-byte units. When the desired instruction or data that caused
the miss is loaded from external memory to the cache, the instruction or data is transferred to the
CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared
to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U
bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache-
update cycle starts after the entry is transferred to the write-back buffer. After the cache completes
its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte
units.
4.3.3 Prefetch Operation
Prefetch Hit: The LRU is updated to indicate that the hit way is the most recently hit way. The
other contents of the cache are not changed. Instructions and data are not transferred from the
cache to the CPU.
Prefetch Miss: Instructions and data are not transferred from the cache to the CPU. The way that
is to be replaced is shown in table 4.2. The other operations are the same as those for a read miss.
4.3.4 Write Access
Write Hit: In a write access in write-back mode, the data is written to the cache and no external
memory write cycle is issued. The U bit of the entry that has been written to is set to 1, and the
LRU is updated to indicate that the hit way is the most recently hit way. In write-through mode,
the data is written to the cache and an external memory write cycle is issued. The U bit of the
entry that has been written to is not updated, and the LRU is updated to indicate that the hit way is
the most recently hit way.
Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the
entry is updated. The way to be replaced is shown in table 4.3. When the U bit of the entry which
is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been
transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set
to 1. The LRU is updated to indicate that the replaced way is the most recently updated way. After
the cache has completed its update cycle, the write-back buffer writes the entry back to the
memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write
miss; the write is only to the external memory.
Rev. 2.00, 09/03, page 102 of 690