HD6417705 Datasheet, PDF (104/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 2.10 Branch Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
BF
disp
10001011dddddddd If T = 0, disp × 2 + PC → PC; –
if T = 1, nop
3/1^* –
BF/S
disp
BT
disp
BT/S
disp
10001111dddddddd Delayed branch,
–
if T = 0, disp × 2 + PC → PC;
if T = 1, nop
10001001dddddddd If T = 1, disp × 2 + PC → PC; –
if T = 0, nop
10001101dddddddd Delayed branch,
–
if T = 1, disp × 2 + PC → PC;
if T = 0, nop
2/1^* –
3/1^* –
2/1^* –
BRA
disp
1010dddddddddddd
Delayed branch, disp × 2 + PC → –
PC
2
–
BRAF
Rm
0000mmmm00100011 Delayed branch,Rm + PC → PC –
2
–
BSR
disp
1011dddddddddddd
Delayed branch, PC → PR, disp –
× 2 + PC → PC
2
–
BSRF
Rm
0000mmmm00000011 Delayed branch, PC → PR, Rm + –
PC → PC
2
–
JMP
@Rm
0100mmmm00101011 Delayed branch, Rm → PC
–
2
–
JSR
@Rm
0100mmmm00001011 Delayed branch, PC → PR, Rm –
→ PC
2
–
RTS
0000000000001011 Delayed branch, PR → PC
–
2
–
Note: * One state when the branch is not executed.
Rev. 2.00, 09/03, page 58 of 690