HD6417705 Datasheet, PDF (192/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

No
ICR1.BLMSK = 1?
Yes
No
NMI?
No
Yes
Program
execution state
ICR1.MAI = 1?
Yes
No _No
NMI = low?
Yes
Interrupt
No
generated?
Yes
SR.BL=0
or sleep mode or software
standby mode?
Yes
NMI?
No
Yes
Level 15
No
interrupt?
Set interrupt source in
INTEVT and INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/MD/RB
bits in SR to 1
Yes
Level 14
No
interrupt?
Yes
I3-I0 level
14 or lower?
Yes
No
Yes
I3-I0 level
13 or lower?
Level 1
No
interrupt?
Yes
No
Yes
I3-I0
level 0?
No
Branch to exception
handler
I3-I0: Interrupt mask bits in status register (SR)
Figure 6.3 Interrupt Operation Flowchart
Rev. 2.00, 09/03, page 146 of 690