HD6417705 Datasheet, PDF (241/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.7 Address/Data Multiplex I/O Interface
The address/data multiplex (MPX) I/O interface can be selected by setting bits TYPE2 to TYPE0
to 010 in CS5BBCR. Do not set this value to the bits in CSnBCR other than those in area 5B,
otherwise the operation of the LSI is not guaranteed. Access timing for the MPX space is shown
below. In the MPX space, CS5B, AH, RD, and WEn signals control the accessing. The basic
access for the MPX space consists of 2 cycles of address output followed by an access to a normal
space.
The address output is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-
impedance state, collisions of addresses and data can be avoided without inserting idle cycles,
even in continuous accesses. Address output is increased to 3 cycles by setting the MPXW bit to 1
in CS5BWCR. The RD/WR signal is output at the same time as the CSn signal; it is high in the
read cycle and low in the write cycle.
The data cycle is the same as that in a normal space access.
Timing charts are shown in figures 7.11, 7.12, and 7.13.
CKIO
A25 to A16
CS5B
RD/WR
Read
Write
AH
RD
D15 to D0
WEn
D15 to D0
BS
DACKn*
Ta1
Ta2
Ta3
T₁
T₂
Address
Address
Data
Data
Note: * The waveform for DACKn is when active low is specified.
Figure 7.11 Access Timing for MPX Space
(Address Cycle No Wait, Data Cycle No Wait)
Rev. 2.00, 09/03, page 195 of 690