HD6417705 Datasheet, PDF (599/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on
reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue
structure and a stored register is shifted at every branch.
Bit
Bit
Name
31
SVF
30 to 28 
27 to 0 BSA27
to BSA0
Initial
Value
R/W
0
R
0
R
Undefined R
Description
BRSR Valid Flag
Indicates whether the branch source address is stored.
When a branch source address is fetched, this flag is
set to 1. This flag is cleared to 0 by reading from BRSR.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
Reserved
These bits are always read as 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.
Rev. 2.00, 09/03, page 553 of 690